\doxysection{DAC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_a_c___type_def}{}\label{struct_d_a_c___type_def}\index{DAC\_TypeDef@{DAC\_TypeDef}}


Digital to Analog Converter.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a394324f0b573837ca15a87127b2a37ea}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a4ccb66068a1ebee1179574dda20206b6}{SWTRIGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_afbfd2855cdb81939b4efc58e08aaf3e5}{DHR12\+R1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a5eb63912e39085e3e13d64bdb0cf38bd}{DHR12\+L1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a3a382d341fb608a04390bacb8c00b0f0}{DHR8\+R1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_ab1f777540c487c26bf27e6fa37a644cc}{DHR12\+R2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a9f612b6b3e065e810e5a2fb254d6a40b}{DHR12\+L2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a3b096b71656f8fb32cd18b4c8b1d2334}{DHR8\+R2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_affa5cc9fe0cc9eb594d703bdc9d9abd9}{DHR12\+RD}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_aea4d055e3697999b44cdcf2702d79d40}{DHR12\+LD}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a03f8d95bbf0ce3a53cb79506d5bf995a}{DHR8\+RD}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a50b4f0b0d2a376f729c8d7acf47864c3}{DOR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a1bde8391647d6422b39ab5ba4f13848b}{DOR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a1d3fd83d6ed8b2d90b471db4509b0e70}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a9394949a84c836614c6010809e8fe52f}{CCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a43da320382d2256a2d3f13c70fa1f356}{MCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_ab0a6020e38c6ea1bf6c23311cd24b1ea}{SHSR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a7d16719e4c287e32872eb5fec7bed27c}{SHSR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_a7c409f086ada3e148621979f7a0267ac}{SHHR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_a_c___type_def_ad2cd6f3c7ab07ff01b38155f94830c06}{SHRR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Digital to Analog Converter. 

\label{doc-variable-members}
\Hypertarget{struct_d_a_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_a_c___type_def_a9394949a84c836614c6010809e8fe52f}\index{DAC\_TypeDef@{DAC\_TypeDef}!CCR@{CCR}}
\index{CCR@{CCR}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR}{CCR}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a9394949a84c836614c6010809e8fe52f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+CCR}

DAC calibration control register, Address offset\+: 0x38 \Hypertarget{struct_d_a_c___type_def_a394324f0b573837ca15a87127b2a37ea}\index{DAC\_TypeDef@{DAC\_TypeDef}!CR@{CR}}
\index{CR@{CR}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a394324f0b573837ca15a87127b2a37ea} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+CR}

DAC control register, Address offset\+: 0x00 \Hypertarget{struct_d_a_c___type_def_a5eb63912e39085e3e13d64bdb0cf38bd}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR12L1@{DHR12L1}}
\index{DHR12L1@{DHR12L1}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR12L1}{DHR12L1}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a5eb63912e39085e3e13d64bdb0cf38bd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR12\+L1}

DAC channel1 12-\/bit left aligned data holding register, Address offset\+: 0x0C \Hypertarget{struct_d_a_c___type_def_a9f612b6b3e065e810e5a2fb254d6a40b}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR12L2@{DHR12L2}}
\index{DHR12L2@{DHR12L2}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR12L2}{DHR12L2}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a9f612b6b3e065e810e5a2fb254d6a40b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR12\+L2}

DAC channel2 12-\/bit left aligned data holding register, Address offset\+: 0x18 \Hypertarget{struct_d_a_c___type_def_aea4d055e3697999b44cdcf2702d79d40}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR12LD@{DHR12LD}}
\index{DHR12LD@{DHR12LD}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR12LD}{DHR12LD}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_aea4d055e3697999b44cdcf2702d79d40} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR12\+LD}

DUAL DAC 12-\/bit left aligned data holding register, Address offset\+: 0x24 \Hypertarget{struct_d_a_c___type_def_afbfd2855cdb81939b4efc58e08aaf3e5}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR12R1@{DHR12R1}}
\index{DHR12R1@{DHR12R1}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR12R1}{DHR12R1}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_afbfd2855cdb81939b4efc58e08aaf3e5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR12\+R1}

DAC channel1 12-\/bit right-\/aligned data holding register, Address offset\+: 0x08 \Hypertarget{struct_d_a_c___type_def_ab1f777540c487c26bf27e6fa37a644cc}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR12R2@{DHR12R2}}
\index{DHR12R2@{DHR12R2}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR12R2}{DHR12R2}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_ab1f777540c487c26bf27e6fa37a644cc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR12\+R2}

DAC channel2 12-\/bit right aligned data holding register, Address offset\+: 0x14 \Hypertarget{struct_d_a_c___type_def_affa5cc9fe0cc9eb594d703bdc9d9abd9}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR12RD@{DHR12RD}}
\index{DHR12RD@{DHR12RD}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR12RD}{DHR12RD}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_affa5cc9fe0cc9eb594d703bdc9d9abd9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR12\+RD}

Dual DAC 12-\/bit right-\/aligned data holding register, Address offset\+: 0x20 \Hypertarget{struct_d_a_c___type_def_a3a382d341fb608a04390bacb8c00b0f0}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR8R1@{DHR8R1}}
\index{DHR8R1@{DHR8R1}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR8R1}{DHR8R1}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a3a382d341fb608a04390bacb8c00b0f0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR8\+R1}

DAC channel1 8-\/bit right aligned data holding register, Address offset\+: 0x10 \Hypertarget{struct_d_a_c___type_def_a3b096b71656f8fb32cd18b4c8b1d2334}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR8R2@{DHR8R2}}
\index{DHR8R2@{DHR8R2}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR8R2}{DHR8R2}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a3b096b71656f8fb32cd18b4c8b1d2334} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR8\+R2}

DAC channel2 8-\/bit right-\/aligned data holding register, Address offset\+: 0x1C \Hypertarget{struct_d_a_c___type_def_a03f8d95bbf0ce3a53cb79506d5bf995a}\index{DAC\_TypeDef@{DAC\_TypeDef}!DHR8RD@{DHR8RD}}
\index{DHR8RD@{DHR8RD}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DHR8RD}{DHR8RD}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a03f8d95bbf0ce3a53cb79506d5bf995a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DHR8\+RD}

DUAL DAC 8-\/bit right aligned data holding register, Address offset\+: 0x28 \Hypertarget{struct_d_a_c___type_def_a50b4f0b0d2a376f729c8d7acf47864c3}\index{DAC\_TypeDef@{DAC\_TypeDef}!DOR1@{DOR1}}
\index{DOR1@{DOR1}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DOR1}{DOR1}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a50b4f0b0d2a376f729c8d7acf47864c3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DOR1}

DAC channel1 data output register, Address offset\+: 0x2C \Hypertarget{struct_d_a_c___type_def_a1bde8391647d6422b39ab5ba4f13848b}\index{DAC\_TypeDef@{DAC\_TypeDef}!DOR2@{DOR2}}
\index{DOR2@{DOR2}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DOR2}{DOR2}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a1bde8391647d6422b39ab5ba4f13848b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+DOR2}

DAC channel2 data output register, Address offset\+: 0x30 \Hypertarget{struct_d_a_c___type_def_a43da320382d2256a2d3f13c70fa1f356}\index{DAC\_TypeDef@{DAC\_TypeDef}!MCR@{MCR}}
\index{MCR@{MCR}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{MCR}{MCR}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a43da320382d2256a2d3f13c70fa1f356} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+MCR}

DAC mode control register, Address offset\+: 0x3C \Hypertarget{struct_d_a_c___type_def_a7c409f086ada3e148621979f7a0267ac}\index{DAC\_TypeDef@{DAC\_TypeDef}!SHHR@{SHHR}}
\index{SHHR@{SHHR}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SHHR}{SHHR}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a7c409f086ada3e148621979f7a0267ac} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+SHHR}

DAC Sample and Hold hold time register, Address offset\+: 0x48 \Hypertarget{struct_d_a_c___type_def_ad2cd6f3c7ab07ff01b38155f94830c06}\index{DAC\_TypeDef@{DAC\_TypeDef}!SHRR@{SHRR}}
\index{SHRR@{SHRR}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SHRR}{SHRR}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_ad2cd6f3c7ab07ff01b38155f94830c06} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+SHRR}

DAC Sample and Hold refresh time register, Address offset\+: 0x4C \Hypertarget{struct_d_a_c___type_def_ab0a6020e38c6ea1bf6c23311cd24b1ea}\index{DAC\_TypeDef@{DAC\_TypeDef}!SHSR1@{SHSR1}}
\index{SHSR1@{SHSR1}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SHSR1}{SHSR1}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_ab0a6020e38c6ea1bf6c23311cd24b1ea} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+SHSR1}

DAC Sample and Hold sample time register 1, Address offset\+: 0x40 \Hypertarget{struct_d_a_c___type_def_a7d16719e4c287e32872eb5fec7bed27c}\index{DAC\_TypeDef@{DAC\_TypeDef}!SHSR2@{SHSR2}}
\index{SHSR2@{SHSR2}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SHSR2}{SHSR2}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a7d16719e4c287e32872eb5fec7bed27c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+SHSR2}

DAC Sample and Hold sample time register 2, Address offset\+: 0x44 \Hypertarget{struct_d_a_c___type_def_a1d3fd83d6ed8b2d90b471db4509b0e70}\index{DAC\_TypeDef@{DAC\_TypeDef}!SR@{SR}}
\index{SR@{SR}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a1d3fd83d6ed8b2d90b471db4509b0e70} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+SR}

DAC status register, Address offset\+: 0x34 \Hypertarget{struct_d_a_c___type_def_a4ccb66068a1ebee1179574dda20206b6}\index{DAC\_TypeDef@{DAC\_TypeDef}!SWTRIGR@{SWTRIGR}}
\index{SWTRIGR@{SWTRIGR}!DAC\_TypeDef@{DAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SWTRIGR}{SWTRIGR}}
{\footnotesize\ttfamily \label{struct_d_a_c___type_def_a4ccb66068a1ebee1179574dda20206b6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DAC\+\_\+\+Type\+Def\+::\+SWTRIGR}

DAC software trigger register, Address offset\+: 0x04 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
